This invention relates to signal mappers, and more particularly to continuous one-to-one nonlinear mapping of digital signals.
A signal mapper is an apparatus that operates on an input signal x and outputs a signal y according to a functional map f:xxe2x86x92y. A signal mapper is linear if signal x1 produces signal y1, signal x2 produces signal y2, and ax1+bx2 produces ay1+by2 for all constant pairs (a,b) and input pairs (x1,x2). Any signal mapper which violates this property is called a nonlinear mapper.
Nonlinear mappers can be employed to implement numerous digital signal processing tasks within communications systems. Power control procedures between base stations and mobile terminals within a cellular network may be based on estimated signal-to-interference plus noise power ratios (SINR). SINR estimates can be mapped to their logarithmic representation by a nonlinear mapper. The logarithmic map stabilizes the variance of an estimated SINR signal and thereby helps improve power control performance and stability. A benefit of improved power control is an increase in cellular network capacity. Automatic gain control (AGC) is another signal processing task that typically employs a nonlinear mapper. For AGC a nonlinear logarithmic mapper maps a many-decade dynamic range input signal to an output signal with a relatively narrow dynamic range, an AGC loop requirement. Source coding is another digital signal processing task that may require a nonlinear mapper. A non-uniform quantizer for source coding can be implemented by first passing a digital signal through a type of nonlinear mapper called a compander. The compander compresses the signal""s amplitude range which is subsequently uniformly quantized. The above digital signal processing tasks and many others such as signal enhancement, noise and interference mitigation, nonlinear pre-emphasis and de-emphasis, cryptography, digital watermarking, square roots, inverse tangents for phase, etc., may employ nonlinear mappings. Methods which implement nonlinear maps in a computationally and power efficient manner are a necessity in current and future communications systems.
Two methods for implementing nonlinear maps for digital signal processing tasks within communications systems are commonly used in prior art. The first method involves storing desired nonlinear map output values in a random-access-memory (RAM) look-up table, one for every possible mapper input value. This method allows a nonlinear mapper output value to be computed quickly if the look-up table is small and is practical for nonlinear maps requiring limited precision and having mapper input and output values within a small domain. However, for many nonlinear maps this method is impractical because it requires too great a RAM to store the look-up table, especially if the nonlinear mapper is implemented on an integrated circuit chip where chip area is a limited resource. The second method for computing a nonlinear map involves implementing a power series expansion to approximate a desired nonlinear map. Although the power series method allows a nonlinear map value to be computed with high precision, it requires a large number of numeric operations to attain high precision and therefore a longer period of time to execute. This negatively affects the time-critical throughput of a digital signal processing task within a communications systems.
A need exists for a nonlinear mapper that can quickly and accurately perform nonlinear maps of digital signals and can be implemented using minimal hardware and power consumption. Additionally, the nonlinear mapper should have the capability to be reconfigured instantaneously allowing a single nonlinear mapper to be utilized for numerous nonlinear maps that may be required in a communications system.
The present invention provides a nonlinear mapper that can implement any continuous one-to-one nonlinear map of baseband or intermediate-frequency digital signals. The mapping method follows a xe2x80x9cdivide-and-conquerxe2x80x9d approach in that a nonlinear map to be implemented is piecewise decomposed into a set of simpler nonlinear component maps. The component maps are implemented using code-enabled feed-forward neural networks (FF-NNs). Each code-enabled feed-forward neural network only operates on samples of a digital input signal that lie in a specified interval of the real-valued number line. Code-enabled FF-NNs are controlled by codewords produced by a scalar quantization encoder. The quantization encoder also controls a multiplexer that directs values produced by the FF-NNs to the nonlinear mapper""s output.
Each code-enabled FF-NN implements a component nonlinear map of a piecewise decomposition as a weighted linear summation of sigmoidal basis functions. The FF-NN apparatus implements the summation in a parallel architecture thereby allowing a nonlinear map to be performed quickly. The apparatus to implement each basis function in the summation employs a simple RAM look-up table. Smoothness properties, symmetry and ordinate ranges of sigmoidal functions allow the basis functions to be implemented using very small RAM look-up tables. Weights associated with basis functions can be changed instantaneously thereby allowing the nonlinear mapper to be easily and quickly reconfigured for numerous nonlinear maps.
The details of an embodiment of the invention are set forth in the accompanying drawings and description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.